Research

A low-loss balun-embedded interconnect for THz heterogeneous system integration (IMS’20)

An interconnect for THz heterogeneous integration is proposed in this work. Two transmission lines deployed on a 40-nm CMOS chip and an IPD carrier, respectively, are coupled together to form a Marchand balun during a flip-chip packaging process. By doing this, the proposed interconnect can provide packaging and balun functions simultaneously. Two interconnects using the proposed idea are demonstrated with measured and simulated insertion loss of 0.9 and 1.4 dB at 169 and 340 GHz, respectively.

A Flip-Chip-Assembled W-Band Receiver in 90-nm CMOS and IPD Technologies (TMTT’19)

A flip-chip-assembled W-band receiver composed of a 90-nm CMOS chip and an integrated-passive-device (IPD) carrier is presented in this paper. The chip which integrates a low-noise amplifier, a single-sideband mixer, a frequency doubler (FD), and a wide-band variable-gain amplifier, is flip-chip packaged to the IPD carrier through a low-loss interconnect. The simulated loss of the interconnect without any compensation network is only 0.95 dB at 94 GHz. The FD can provide differential output without any additional lossy balun required, effectively increasing the FD output power, and hence relaxing the local oscillator generation circuit design. The experimental results show that the proposed packaged receiver can provide a variable gain from 11.3 to 48.2 dB, while having an input 1-dB compression point from −43.7 to −29 dBm as the RF frequency is 90 GHz. The intermediate bandwidth and minimum noise figure can be 1.0 GHz and 7.8 dB, respectively. The proposed receiver only consumes 73.9 mW from a 1.2-V supply. As compared with prior works, the proposed receiver exhibits higher gain, lower noise, and lower power dissipation even though a less-advanced 90-nm CMOS technology is adopted. To the best of the authors’ knowledge, this is the first W-band CMOS receiver assembled on an IPD carrier reported thus far.

Single Flip-Chip Packaged Dielectric Resonator Antenna for CMOS Terahertz Antenna Array Gain Enhancement (IEEE Access’19)

A single dielectric resonator antenna (DRA) capable of enhancing the antenna gain of each element of a 2x2 terahertz (THz) antenna array realized in a 0.18-um CMOS technology is proposed in this paper. The DRA implemented in a low-cost integrated-passive-device technology is flip-chip packaged onto the CMOS antenna array chip through low-loss gold bumps. By designing the DRA to work at the higher order mode of TE3,delta,9, only a single DRA, instead of conventionally needing four DRAs, is required to simultaneously improve the antenna gain of each element of the 22 antenna array. This not only simplifies the assembly process, but it can also reduce the assembly cost. Moreover, the DRA can provide great antenna gain enhancement because of being made of high-resistivity silicon material and higher order mode operation. The simulated antenna gain of each on-chip patch antenna of the 22 CMOS antenna array can be increased from 0.1 to 8.6 dBi at 339 GHz as the DRA is added. To characterize the proposed DRA, four identical power detectors (PDs) are designed and integrated with each element of the 2x2 THz antenna array. By measuring the voltage responsivity of each PD output, the characteristics of each antenna of the antenna array with the proposed DRA, including the gain enhancement level and radiation pattern, can be acquired. The measurement results match well with the simulated ones, verifying the proposed DRA operation principle. The four PDs with the proposed DRA are also successfully employed to demonstrate a THz imaging system at 340 GHz. To the best of our knowledge, the proposed DRA is the one with the highest order operation mode at THz frequencies reported thus far.

A balun-less frequency multiplier with different output by current flow manipulation (TVLSI’18)

A balunless frequency doubler (FD) architecture which can provide differential output without any additional balun required is proposed in this paper. The architecture manipulates the desired second-harmonic currents around the doubler core by a multifunction network to avoid any leakage current path from the output current loop. Therefore, the output currents extracted from the same current loop can have the same amplitude and phase. As the output currents flow into and out of the same loads, respectively, the induced output voltages can be perfectly differential without needing to add a balun. A 60-GHz FD realized in a 90-nm CMOS technology is designed to verify the proposed FD architecture. The measured amplitude and phase imbalances of the differential output are only 0.2 dB and 0.5°, respectively, while providing −5.5-dB conversion gain at an output frequency of 60 GHz. The proposed FD only consumes 15.9 mW from a 1-V supply. The proposed doubler architecture can be theoretically extended to realize a frequency multiplier with a multiplication factor larger than 2.

A 7.1-mW K/Ka-band mixer with configurable bondwire resonators in 65-nm CMOS (TVLSI’17)

A low-power K/Ka-band mixer with configurable capability is proposed in this work. The mixer integrates a broadband transconductor stage, bondwire resonators, a broadband LO balun, and a broadband switching stage. The bondwire resonators not only work as a balun for single-ended to differential conversion between the transconductor stage and the switching stage, but they can also be configured to have two or three resonators by controlling the number of bonding bondwires during the chip packaging process. These two and three resonators intentionally designed to have weak and strong magnetic couplings with each other enable the mixer to exhibit narrowband and broadband frequency responses, respectively. Realized in a 65-nm low-power CMOS technology, the mixers configured to have two and three resonators show measured conversion gains of 17.2 and 15.5 dB while giving 3-dB and 5-dB bandwidths from 22.5 to 28.5 GHz and 21.5 to 32.5 GHz, respectively. The measured input third-order intercept points, noise figures, and port-to-port isolations of the mixers with two and three resonators are better than -2.7 and -1.9 dBm, 11.2 and 11 dB, 25.6 and 25.7 dB, within the bandwidths, respectively. The mixer only consumes 7.1 mW from a 1.2 V supply.

A compact 0.9-/2.6-GHz dual-band RF energy harvester using SiP technique (MWCL’17)

A compact dual-band radio-frequency (RF) energy harvester (EH) composed of matching networks, band-pass and band-stop filters (BPF/BSF), and rectifiers, using a system-in-package technique is proposed in this letter. The matching networks and BPF/BSF are realized on a low-loss integrated-passive-device (IPD) carrier while the rectifiers are implemented in a 0.18-μm CMOS technology. The CMOS chip is flipped and bonded onto the IPD carrier through low-loss gold bumps. The proposed BPF/BSF can provide zeros and poles to pass and stop signals, respectively, allowing dual-band operation. Moreover, high-Q IPD passive components are employed to design the matching networks and the filters. This not only gives a compact solution, but higher impedance transformation ratio between the source resistance and the rectifier input impedance also becomes feasible, which provides higher voltage gain to greatly enhance the RF-to-dc conversion efficiency. The proposed RF EH can give measured output voltage of 1.35 and 1.0 V with RF-to-dc conversion efficiency of 12.6 and 7.0% at 0.93 and 2.63 GHz, respectively, as the input power is -15.4 dBm and the load resistance is 500 kΩ. The EH only occupies an area of 11.6 mm2.

340-GHz low-cost and high-gain on-chip higher order mode dielectric resonator antenna for THz applications (TTST’17)

A low-cost and high-gain on-chip THz dielectric resonator antenna (DRA) is proposed in this work. The DRA consists of a low-loss dielectric resonator (DR) made of high-resistivity silicon material and an on-chip feeding patch realized in a 0.18-μm CMOS technology for exciting the desired electromagnetic (EM) mode. The DR can be easily fabricated to the required dimension by wafer dicing of a 2-inch silicon wafer. With a 500-μm thick DR, a higher-order mode of TEδ,1,7 can be excited, which greatly enhances the antenna gain. Such higher-order mode operation also provides a reliable design. If a fundamental mode is selected, the DR thickness is around 100 μm at THz frequencies, which not only requires additional wafer thinning process, but the wafer is also easily broken during the fabrication process. The feeding patch is used to excite the TEδ,1,7 mode. Moreover, its ground plane also prevents the EM field from leaking into the lossy CMOS silicon substrate, which improves the antenna efficiency. The simulated antenna gain can be 7.9 dBi while providing radiation efficiency of 74% at 341 GHz with 7.3% bandwidth. To characterize the DRA performance, an identical CMOS imager is designed to be integrated with the proposed DRA and an on-chip patch antenna, respectively. By comparing the measured responsivity of these two imagers, the gain improvement of the DRA over the on-chip patch antenna can be obtained. Three samples are measured to evaluate the robustness of the proposed antenna over process variation. The measured results show that the maximum gain improvement of 6.7 dB can be acquired at 327 GHz. The proposed DRA with the integrated CMOS imager is also employed to successfully demonstrate a THz transmissive imaging system at 327 GHz. To the best of authors’ knowledge, this is first higher-order mode DRA working at THz frequencies.

A 340-GHz heterodyne receiver front-end in 40-nm CMOS for THz biomedical imaging applications (TTST’16)

A low-power and high-performance 340-GHz heterodyne receiver front-end (RFE) optimized for terahertz (THz) biomedical imaging applications is proposed in this work. The THz RFE consists of an on-chip patch antenna, a single-balanced mixer, and a triple-push harmonic oscillator. The oscillator adopts a proposed harmonic oscillator architecture which can provide differential output by extracting output signals from the same current loop without any additional balun required. The mixer biased in the subthreshold region is designed not only to have high conversion gain and low noise figure by choosing the output intermediate frequency well above the flicker-noise corner frequency, but the required local oscillator (LO) power can also be as low as -11 dBm. Such a low demand on the LO power makes the proposed mixer very suitable for THz applications in which the achievable LO power is very limited. The impact of unavoidable slots for passing design-rule checks on the performance of an on-chip patch antenna is also presented. The proposed THz RFE is implemented in a 40-nm digital CMOS technology. The measured voltage conversion gain is -1.7 dB at 335.8 GHz while the mixer and the oscillator only consume 0.3 mW and 52.8 mW, respectively, from a 1.1 V supply. The proposed THz RFE is employed to set up a THz transmissive imaging system which can provide spatial resolution of 1.4 mm.